The present invention relates to a semiconductor integrated circuit having a nonvolatile semiconductor memory device and, more particularly, to a system for protecting stored data.
This application is based on Japanese Patent Application No. 8-349036, filed Dec. 26, 1996, the content of which is incorporated herein by reference.
In the field of nonvolatile semiconductor memory devices, an electrically programmable nonvolatile semiconductor memory device using an FETMOS memory cell having a floating gate is known as an EEPROM. The memory cell array of an EEPROM of this type is formed by arranging memory cells at intersections of row lines (word lines) and row lines (bit lines), which cross each other. In a general EEPROM, two memory cells share a drain to which a row line is connected.
In a NAND-type EEPROM, the number of contacts between drains and row lines is reduced to increase the integration density of the memory cell. The NAND-type EEPROM includes unit cells (to be referred to as NAND cells hereinafter) each comprising a plurality of memory transistors which are connected in series. The memory cell array of the NAND-type EEPROM is constituted by arranging NAND cells at intersections of row lines (including selection gate lines and control gate lines) and row lines. A plurality of NAND cells, e.g., two NAND cells share a drain to which a row line is connected.
In the NAND cell, after electrons are simultaneously discharged from the floating gates of memory elements to erase data (simultaneous erase), electrons are injected into only floating gates of selected memory elements in accordance with data to be written, thereby selectively writing the data.
In the simultaneous erase mode, the voltages of the control gates of all memory elements are set at "L", and the voltage of the well is set at "H", so electrons in the floating gates of the memory elements are extracted to the well.
In the selective write mode, data is sequentially written in the memory elements from the source side to the drain side. In this case, the voltages of the drains of memory elements selected to write data are set at "L" or an intermediate level between "L" and "H" in accordance with the data to be written, and the voltages of control gates are set at "H". If the drain voltages are at "L", electrons are injected into the floating gates.
In non-selected memory elements on the drain side of the selected memory element, the voltage of the control gate is set at almost the same level as that of the intermediate voltage applied to the drain. This is because, in a MOSFET, of the voltage applied to the drain, only a voltage obtained by subtracting the threshold voltage of the MOSFET from the voltage applied to the gate is transmitted to the source.
In a read mode, a power supply voltage Vcc (=4.5 to 5.5 V) is applied to the control gate of each non-selected memory element to turn on the non-selected memory element independently of whether electrons are injected into the floating gate. A voltage of 0 V is applied to memory elements selected to read out data. Each memory element selected to read out data is turned on or off depending on whether electrons are injected into the floating gate. With this operation, data stored in the memory element is read out.
In such a conventional NAND-type EEPROM, confidential data stored in the EEPROM cannot be read out unless a specific signal is input. Anyone can access the confidential data stored in the EEPROM so that there arises a problem in security. The security is very important if the EEPROM is used as a memory card. That is, an operation of protecting stored data (read-inhibiting operation) cannot be performed. This applies not only to the NAND-type EEPROM but also to a general NOR-type EEPROM, a NAND-type EEPROM having NOR cells, and a DINOR-type EEPROM.
The conventional nonvolatile semiconductor memory device cannot perform an operation of enabling a data read only when a predetermined condition for reading out data is satisfied, and otherwise, inhibiting the data read.